This invention relates to memory access operations and, more particularly, to power supply aware memory access operations in integrated circuits.
Integrated circuits often contain memory elements. Typical memory elements are based on cross-coupled inverters (latches) and are used to store data. Each memory element can store a single bit of data.
Memory elements are often used to store configuration data in integrated circuits. For example, memory elements may be used to store configuration data in programmable logic device integrated circuits. Programmable logic devices are a type of integrated circuit that can be customized in relatively small batches to implement a desired logic design. In a typical scenario, a programmable logic device manufacturer designs and manufactures un-customized programmable logic device integrated circuits in advance. Later, a logic designer uses a logic design system to design a custom logic circuit.
The logic design system uses information on the hardware capabilities of the manufacturer's programmable logic devices to help the designer implement the logic circuit using the resources available on a given programmable logic device.
The logic design system creates configuration data based on the logic designer's custom design. When the configuration data is loaded into the memory elements of one of the programmable logic devices, it programs the logic of that programmable logic device so that the programmable logic device implements the designer's logic circuit. The use of programmable logic devices can significantly reduce the amount of effort required to implement a desired integrated circuit design.
Conventional programmable logic device memory elements are powered at a constant positive power supply voltage. However, on-die variability noise or other variations in the power supply to the memory elements and related read/write circuitry on the programmable logic device may cause the ability to read and write to some memory elements to become unreliable.
An operational logic circuit implemented in the programmable logic device may cause at least a portion of the noise in the power supply voltage. The noise in the power supply voltage may further increase due to unavoidable resonances in the power-distribution network which are caused by internal and external parasitic capacitances. These resonances are typically in the 10 MHz to 100 MHz range, resulting in noise variations with periods ranging from 10 ns to 100 ns. These noise variations may cause dips in the power supply voltage that fall below the average power supply voltage, causing memory access operations to become marginal or even fail.